The invention relates in general to a multiple bus architecture associated with a signal processor and in particular to a memory storage device for use with such a multibus architecture.
To achieve a relatively high throughput of data in signal processors, these processors often include multiple connected read/write buses through which a single data memory storage device may be accessed simultaneously. Control of memory addresses is typically implemented through read/write buses by alternately transmitting addresses and data, or by transmitting addresses through a separate address bus apart from a data bus.
Where these systems involve one or multiple data memories and multiple buses (i.e., a multibus architecture), the actual memory/bus connection is usually achieved in a manner which is relatively disadvantageous. Two approaches are commonly utilized to achieve relatively efficient memory access to store data in the memory or to read data from the memory. Either a multi-port memory is used which has multiple memory connections to access different buses, or the various buses are connected to mutually independent memory blocks.
The first approach has the disadvantage that a multi-port memory is more complex and expensive to implement than a single-port memory. The second approach has the disadvantage that separation of the memory blocks negatively affects program flexibility and execution speed. For example, the memory partitioning must be defined within the program code, a capability which is often not provided in high-level languages such as C.
What is needed is a memory storage device for a multibus architecture which enables more efficient memory access.